Wiring board and semiconductor device

ABSTRACT

A method of fabricating a wiring board includes forming a resist layer, such as a solder or plating resist layer, defining an opening portion on a support board such that a portion of the support board is exposed. An electrode is formed directly on the support board within the opening portion, and the plating resist layer, when used, is removed. An insulating layer is formed on the electrode, as well as the support board or solder resist layer, and a wiring portion connected to the electrode at the insulating layer is also formed. A solder resist layer having an opening portion is then formed on the wiring portion, and the support board is removed to expose a surface of the electrode or a surface of the electrode and insulating layer. Another solder resist layer having an opening portion may then be formed on the exposed surface of the insulating layer.

The present application claims foreign priority based on Japanese PatentApplication No. 2005-159993, filed May 31, 2005 and Japanese PatentApplication No. 2006-014199, filed Jan. 23, 2006, the contents of whichare incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Technical Field

The present disclosure relates to a method of fabricating a wiring boardformed on a support board and a method of fabricating a semiconductordevice constituted by mounting a semiconductor chip on the wiring board.

2. Related Art

In recent years, high density formation and thin-sized formation of asemiconductor chip has been promoted in accordance with high speedformation and high integrated formation of a semiconductor device andhigh density formation/thin-sized formation are requested similarly to awiring board connected with the semiconductor chip.

In order to deal with high density formation of a wiring of the wiringboard and thin-sized formation thereof, in recent years, the maincurrent is constituted by a method of forming a wiring board by aso-to-speak build up method. When a multilayer wiring board is formed bythe build up method, the multilayer wiring board is formed as follows.

First, a build up layer comprising an insulating resin layer is formedon a support board (core board) having a pertinent rigidity, a via holeis formed at the build up layer, thereafter, a via plug is formed at thevia hole by a plating method and a pattern wiring connected to the viaplug is formed. Thereafter, by repeating the steps, a multilayer wiringboard can be formed by the build up method.

The build up layer (insulating resin layer) comprises a soft materialof, for example, thermosetting epoxy resin or the like and therefore, inorder to maintain flatness of the build up layer, there is adopted amethod of forming the build up layer on a support board having apertinent rigidity (For example, See Japanese patent documentJP-A-2002-198462).

However, it is requested to further subject the wiring board formed bythe build up method to thin-sized formation and therefore, there hasbeen proposed a structure of removing the support board, or a wiringboard having a so-to-speak coreless structure.

However, when the wiring board is constituted by the coreless structure,a rigidity of the wiring board is reduced. Therefore, there poses aproblem which becomes difficult when after removing the support board orexfoliating the wiring board from the support board, a step oflaminating a necessary layer on the wiring board and working the wiringboard is provided. An example of the step will be explained as follows.

For example, water absorbing performance of the build up layer is highand in a state of exposing a surface thereof, there is brought about aconcern in insulation reliability over a long period of time and it ispreferable to cover the surface by a protecting layer of a solder resistlayer or the like. However, according to the build up method of therelated-art, when the solder resist layer covering the surface of thebuild up layer formed right above the support board is formed, it isnecessary to remove the support board or exfoliate the build up layerfrom the support board.

In this case, it is necessary to carry the wiring board in the midst ofworking in which the support board is removed and the rigidity isreduced to pose a problem that a concern of damaging the wiring board isincreased. Further, when the solder resist layer is formed at the buildup layer after removing the support board, the rigidity is insufficientand therefore, there is a case of posing a problem in flatness of thewiring board.

Therefore, there is a case in which it is difficult to excellentlymaintain accuracy of working the solder resist layer. The problem of theaccuracy of working the solder resist layer becomes significantparticularly when a wiring board in correspondence with a high functionsemiconductor chip in recent years which is subjected to highdensity/high integrated formation.

SUMMARY OF THE INVENTION

The disclosure below describes a method of forming a novel and usefulwiring board resolving the above-described problem.

The disclosure describes a method of fabricating a wiring board and amethod of fabricating a semiconductor device constituted by mounting thesemiconductor device on the wiring board.

In a first aspect, the disclosure describes a method of fabricating awiring board comprising a first step of forming a first solder resistlayer having a first opening portion on a support board, a second stepof forming an electrode at the first opening portion, a third step offorming an insulating layer on the electrode and forming a wiringportion connected to the electrode at the insulating layer, a fourthstep of forming a second solder resist layer having a second openingportion on the wiring portion, and a fifth step of removing the supportboard.

According to the method of fabricating the wiring board, there can beprovided the method of fabricating the wiring board capable ofconstituting thin-sized formation and capable of dealing with highdensity wiring.

Further, when the support board comprises a conductive material and theelectrode is formed by an electrolytic plating method, the electrode canbe formed by an easy method and with excellent working accuracy.

Further, when the second step includes a step of forming a recessportion by etching the support board and the electrode is formed tocorrespond to the recess portion, the electrode can be constituted by astructure of being projected from the first solder resist layer.

Further, when the second step includes a step of forming an electrodeheight adjusting layer at the first opening portion and the electrode isformed on the electrode height adjusting layer, the electrode can beconstituted by a structure of being recessed from the first solderresist layer.

Further, when in the fifth step, the electrode height adjusting layer isremoved along with the support board, the step of removing the electrodeheight adjusting layer becomes simple, which is preferable.

Further, when the support board and the height adjusting layer compriseCu or a Cu alloy, the support and the height adjusting layer can beremoved by the same etching solution.

Further, when a thickness of the electrode height adjusting layer isequal to or larger than a thickness of the first solder resist layer,the electrode can be constituted by a structure of being embedded in theinsulating layer.

Further, when an area of the electrode is larger than an area of thefirst opening portion, a strength of the electrode is improved.

Further, when there is provided the method of fabricating a wiringboard, further comprising a sixth step of pasting the support boardtogether with a separate support board before the first step, a seventhstep of forming a third solder resist layer having a third openingportion on the separate support board, an eighth step of forming aseparate electrode at the third opening portion, a ninth step of forminga separate insulating layer to cover the separate electrode and forminga separate wiring portion connected to the separate electrode at theseparate insulating layer, a tenth step of forming a fourth solderresist layer having a fourth opening portion to cover the separatewiring portion, and an eleventh step of removing the separate supportboard, the wiring boards can be formed at both of the support board andthe separate support board.

Further, in a second aspect of the invention, the disclosure describes amethod of fabricating a semiconductor device using the method offabricating a wiring board, characterized in further comprising amounting step of mounting a semiconductor chip to be electricallyconnected to the wiring portion from the second opening portion afterthe fourth step.

According to the method of fabricating a semiconductor device, there canbe provided the method of fabricating a semiconductor device capable ofconstituting thin-sized formation and capable of dealing with highdensity wiring.

Further, when the method further comprises a step of etching the supportboard exposed from the first opening portion and forming an externalconnecting terminal at the etched support board after the first step, aportion of connecting the semiconductor device and an object to beconnected is easily formed.

Further, in a third aspect of the invention, the disclosure describes amethod of fabricating a semiconductor device characterized in a methodof fabricating a semiconductor device using the method of fabricatingthe wiring board, further comprising a mounting step of mounting asemiconductor chip to be electrically connected to the wiring portion byway of the electrode after the fifth step.

According to the method of fabricating a semiconductor device, there canbe provided the method of fabricating a semiconductor device capable ofconstituting thin-sized formation and capable of dealing with highdensity wiring.

Further, when the method further comprises a step of etching the supportboard exposed from the first opening portion and forming a semiconductorconnecting terminal at the etched support board after the first step,wherein the semiconductor chip is mounted on the semiconductor chipconnecting terminal, the semiconductor chip is easily mounted.

One or more of the following advantages may be present in someimplementations. For example, there can be provided the method offabricating a wiring board capable of constituting thin-sized formationand capable of dealing with high density wiring and the method offabricating a semiconductor device constituted by mounting thesemiconductor device on the wiring board.

Further, the wiring board which is constituted by a coreless structure,both sides of which are covered by the solder resist layers and which isformed by a build up method can be provided.

Further, the wiring board constituted by the coreless structure andsubjected thin-sized formation can be formed, further, the first openingportion is formed in a state in which flatness of the first resist layeris excellent and therefore, accuracy of working the first openingportion becomes excellent. Therefore, the wiring board capable ofdealing with a high density wiring, and a semiconductor deviceconstituted by mounting the semiconductor device on the wiring board canbe fabricated.

Other features and advantages may be apparent from the followingdetailed description, the accompanying drawings and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a view showing a method of fabricating a wiring boardaccording to exemplary, non-limiting Embodiment 1 (part 1).

FIG. 1B is a view showing the method of fabricating the wiring boardaccording to exemplary, non-limiting Embodiment 1 (part 2).

FIG. 1C is a view showing the method of fabricating the wiring boardaccording to exemplary, non-limiting Embodiment 1 (part 3).

FIG. 1D is a view showing the method of fabricating the wiring boardaccording to exemplary, non-limiting Embodiment 1 (part 4).

FIG. 1E is a view showing the method of fabricating the wiring boardaccording to exemplary, non-limiting Embodiment 1 (part 5).

FIG. 2A is a view showing a method of fabricating a wiring boardaccording to exemplary, non-limiting Embodiment 2 (part 1).

FIG. 2B is a view showing the method of fabricating the wiring boardaccording to exemplary, non-limiting Embodiment 2 (part 2).

FIG. 2C is a view showing the method of fabricating the wiring boardaccording to exemplary, non-limiting Embodiment 2 (part 3).

FIG. 2D is a view showing the method of fabricating the wiring boardaccording to exemplary, non-limiting Embodiment 2 (part 4).

FIG. 2E is a view showing the method of fabricating the wiring boardaccording to exemplary, non-limiting Embodiment 2 (part 5).

FIG. 2F is a view showing the method of fabricating the wiring boardaccording to exemplary, non-limiting Embodiment 2 (part 6).

FIG. 3A is a view showing a method of fabricating a wiring boardaccording to exemplary, non-limiting Embodiment 3 (part 1).

FIG. 3B is a view showing the method of fabricating the wiring boardaccording to exemplary, non-limiting Embodiment 3 (part 2).

FIG. 3C is a view showing the method of fabricating the wiring boardaccording to exemplary, non-limiting Embodiment 3 (part 3).

FIG. 3D is a view showing the method of fabricating the wiring boardaccording to exemplary, non-limiting Embodiment 3 (part 4).

FIG. 3E is a view showing the method of fabricating the wiring boardaccording to exemplary, non-limiting Embodiment 3 (part 5).

FIG. 3F is a view showing the method of fabricating the wiring boardaccording to exemplary, non-limiting Embodiment 3 (part 6).

FIG. 4A is a view showing a method of fabricating a wiring boardaccording to exemplary, non-limiting Embodiment 4 (part 1).

FIG. 4B is a view showing the method of fabricating the wiring boardaccording to exemplary, non-limiting Embodiment 4 (part 2).

FIG. 4C is a view showing the method of fabricating the wiring boardaccording to exemplary, non-limiting Embodiment 4 (part 3).

FIG. 4D is a view showing the method of fabricating the wiring boardaccording to exemplary, non-limiting Embodiment 4 (part 4).

FIG. 4E is a view showing the method of fabricating the wiring boardaccording to exemplary, non-limiting Embodiment 4 (part 5).

FIG. 4F is a view showing the method of fabricating the wiring boardaccording to exemplary, non-limiting Embodiment 4 (part 6).

FIG. 5 is a view showing a method of fabricating a wiring boardaccording to exemplary, non-limiting Embodiment 5.

FIG. 6A is a view showing a method of fabricating a semiconductor deviceaccording to exemplary, non-limiting Embodiment 6 (part 1).

FIG. 6B is a view showing the method of fabricating the semiconductordevice according to exemplary, non-limiting Embodiment 6 (part 2).

FIG. 6C is a view showing the method of fabricating the semiconductordevice according to exemplary, non-limiting Embodiment 6 (part 3).

FIG. 6D is a view showing the method of fabricating the semiconductordevice according to exemplary, non-limiting Embodiment 6 (part 4).

FIG. 6E is a view showing the method of fabricating the semiconductordevice according to exemplary, non-limiting Embodiment 6 (part 5).

FIG. 6F is a view showing the method of fabricating the semiconductordevice according to exemplary, non-limiting Embodiment 6 (part 6).

FIG. 7 is a view showing a method of fabricating a wiring boardaccording to exemplary, non-limiting Embodiment 7.

FIG. 8A is a view showing a method of fabricating a semiconductor deviceaccording to exemplary, non-limiting Embodiment 8 (part 1).

FIG. 8B is a view showing the method of fabricating the semiconductordevice according to exemplary, non-limiting Embodiment 8 (part 2).

FIG. 9A is a view showing a method of fabricating a semiconductor deviceaccording to exemplary, non-limiting Embodiment 9 (part 1).

FIG. 9B is a view showing the method of fabricating the semiconductordevice according to exemplary, non-limiting Embodiment 9 (part 2).

FIG. 9C is a view showing the method of fabricating the semiconductordevice according to exemplary, non-limiting Embodiment 9 (part 3).

FIG. 9D is a view showing the method of fabricating the semiconductordevice according to exemplary, non-limiting Embodiment 9 (part 4).

FIG. 9E is a view showing the method of fabricating the semiconductordevice according to exemplary, non-limiting Embodiment 9 (part 5).

FIG. 9F is a view showing the method of fabricating the semiconductordevice according to exemplary, non-limiting Embodiment 9 (part 6).

FIG. 10A is a view showing a method of fabricating a semiconductordevice according to exemplary, non-limiting Embodiment 10 (part 1).

FIG. 10B is a view showing the method of fabricating the semiconductordevice according to exemplary, non-limiting Embodiment 10 (part 2).

FIG. 10C is a view showing the method of fabricating the semiconductordevice according to exemplary, non-limiting Embodiment 10 (part 3).

FIG. 10D is a view showing the method of fabricating the semiconductordevice according to exemplary, non-limiting Embodiment 10 (part 4).

FIG. 10E is a view showing the method of fabricating the semiconductordevice according to exemplary, non-limiting Embodiment 10 (part 5).

FIG. 10F is a view showing the method of fabricating the semiconductordevice according to exemplary, non-limiting Embodiment 10 (part 6).

FIG. 11A is a view showing a method of fabricating a wiring boardaccording to exemplary, non-limiting Embodiment 11 (part 1).

FIG. 11B is a view showing the method of fabricating the wiring boardaccording to exemplary, non-limiting Embodiment 11 (part 2).

FIG. 11C is a view showing the method of fabricating the wiring boardaccording to exemplary, non-limiting Embodiment 11 (part 3).

FIG. 11D is a view showing the method of fabricating the wiring boardaccording to exemplary, non-limiting Embodiment 11 (part 4).

FIG. 11E is a view showing the method of fabricating the wiring boardaccording to exemplary, non-limiting Embodiment 11 (part 5).

FIG. 11F is a view showing the method of fabricating the wiring boardaccording to exemplary, non-limiting Embodiment 11 (part 6).

DETAILED DESCRIPTION OF THE INVENTION

Next, embodiments of the invention will be explained in reference to thedrawings.

Exemplary, Non-Limiting Embodiment 1

FIG. 1A through FIG. 1E are views showing a method of fabricating awiring board according to exemplary, non-limiting Embodiment 1 of theinvention in accordance with a procedure thereof.

First, at step shown in FIG. 1A, a solder resist layer 102 comprising aphotosensitive resin material is formed on a support board 101comprising a conductive material of, for example, Cu or the like by, forexample, a screen printing method. In this case, the solder resist layer102 can also be formed by a method of laminating or coating, forexample, a film-like resist material.

Next, ultraviolet ray is irradiated to the solder resist layer 102 byway of a mask pattern (not illustrated) to expose to thereby pattern thesolder resist layer 102 and form an opening portion 102A. There isbrought about a state of exposing the support board 101 from the openingportion 102A.

Next, at a step shown in FIG. 1B, by electrolytic plating constitutingan electricity conducting path by the support board 101, an electrode103 comprising, for example, Au/Ni is formed on the support board 101 tobe embedded in the opening portion 102A. Further, the electrodecomprising Au/Ni signifies an electrode constituted by laminating an Aulayer and an Ni layer, formed such that Au is disposed on a surface side(connecting face) when the wiring board is finished (the same asfollows). In this case, when the support board 101 comprises aconductive material, the electrode 103 can be formed by electrolyticplating and it is further preferable when the support board 101comprises a conductive material having low resistance of Cu or the like.

Next, at a step shown in FIG. 1C, an insulating layer (build up layer)104 comprising, for example, thermosetting epoxy resin is formed on thesolder resist layer 102 and on the electrode 103. Next, a via hole isformed at the insulating layer 104 by, for example, laser.

Next, a via plug 105 is formed at the via hole and a pattern wiring 106connected to the via plug 105 is formed on the insulating layer 104 by,for example, a semiadditive method. In this case, it is preferable toform a seed layer on the insulating layer 104 by electroless plating andthereafter form the via plug 105 on the pattern wiring 106 byelectrolytic plating. In this way, a wiring layer comprising the viaplug 105 and the pattern wiring 106 is formed.

Next, at a stop shown in FIG. 1D, a solder resist layer 107 is formed onthe insulating layer 104 to cover the pattern wiring 106 by, forexample, a screen printing method. Next, ultraviolet ray is irradiatedto the solder resist layer by way of a mask pattern (not illustrated) tobe exposed to thereby pattern the solder resist layer 107 and form anopening portion 107A. There is brought about a state of exposing aportion of the pattern wiring 106 from the opening portion 107A.

Next, in a step shown in FIG. 1E, the support board 101 is removed, forexample, wet etching to form a wiring board 100.

According to the board 100, the electrode 103 is disposed on a side ofbeing connected to an external connected apparatus of, for example, amother board or the like (so-to-speak land side) and the pattern wiring106 exposed from the opening portion 107A is connected with, forexample, a semiconductor chip. In this case, the electrode 103 may beformed with, for example, a solder ball or the like. Further, thepattern wiring 106 exposed from the opening portion 107A may be formedwith, for example, an electrode comprising Au/Ni, or a solder ball, or asolder layer for reflow or the like.

According to the embodiment, one of characteristics thereof resides inthat prior to forming the insulating layer 104, the solder resist layer102 is formed on the support board 101. Therefore, the wiring board bythe build up method which is constituted by the coreless structure andboth sides of which are covered by the solder resist layer can beformed.

In this case, there is achieved an effect of capable of protecting theboth sides of the insulating layer 104 by the solder resist layers,reducing a difference between stresses applied on the both sides of theinsulating layer 104 and restraining the wiring board from being warped.

Further, in the case of the embodiment, the opening portion 107A isformed in a state of supporting the solder resist layer 107 by thesupport board 101 and therefore, when the opening portion 107A isformed, flatness of the solder resist layer 107 is excellent. Therefore,accuracy of working the opening portion 107A becomes excellent and theopening portion 107A can be formed by a fine shape and a fine pitch.

In a semiconductor chip of the recent years, high integratedformation/high density wiring formation are progressed, also at aportion of connecting a semiconductor chip and a wiring board, finepitch formation and high density wiring formation are progressed andtherefore, particularly, accuracy of positioning the opening portion107A and working accuracy of a shape thereof are needed. According tothe method of fabricating the wiring board according to the embodiment,the wiring board in correspondence with the requests and incorrespondence with fine pitch formation/high density wiring formationcan be formed.

Further, according to the method of fabricating the wiring boardaccording to the embodiment, a so-to-speak coreless structure isrealized by removing the support board and thin-sized formation of thewiring board is realized in correspondence with the high density wiring.

Further, according to the wiring board according to the embodiment, theelectrode 103 is disposed on a side of connecting an external apparatusof a mother board or the like (so-to-speak land side). Therefore, anarea (opening diameter) of the opening portion 102A becomes larger thanan area (opening diameter) of the opening portion 107A. For example,there is a large difference between the opening diameters such that theopening diameter of the opening portion 107A connected with thesemiconductor chip is about 80 μm through 100 μm, the opening diameterof the opening portion 102A connected with the mother board or the likeis about 0.5 mm through 1 mm.

For example, when the large opening portion is formed, in the case ofusing laser, a problem of taking time is posed. According to theembodiment, patterning of the opening portion 102A is carried out bysensitizing and the opening portion can be formed more swiftly than inthe case of laser.

Further, by repeatedly executing the step shown in FIG. 1C beforeforming the solder resist layer 107, the wiring board having amultilayer wiring structure can be formed.

For example, as materials of constituting the solder resist layers 102,107, epoxy acrylic species resin, epoxy species resin, acrylic speciesresin can be used. Further, the method of patterning the solder resistlayers 102, 107 is not limited to the method by exposure/developmentdescribed above. For example, a solder resist layer formed (patterned)with an opening portion may be formed by a screen printing method. Inthis case, a material other than a photosensitive material can be usedfor the solder resist layer.

Further, although according to the embodiment, thicknesses of theelectrode 103 the solder resist layer 102 are substantially the same,the invention is not limited thereto but the electrode 103 can bemodified or changed variously as shown below as necessary.

Exemplary, Non-Limiting Embodiment 2

FIG. 2A through FIG. 2F are views showing a method of fabricating awiring board according to exemplary, non-limiting Embodiment 2 of theinvention in accordance with a procedure thereof. Incidentally, portionsin the drawings explained above are attached with the same referencenotations and an explanation thereof will be omitted. Further, a portionwhich is not particularly explained can be formed by a method similar tothat in the case of exemplary, non-limiting Embodiment 1.

A step shown in FIG. 2A is similar to the step shown in FIG. 1A, thesolder resist layer 102 is formed on the support board 101, and theopening portion 102A is formed at the solder resist layer 102.

Next, in a step shown in FIG. 2B, a recess portion 101A is formed byetching the support board 101 exposed from the opening portion 102A.

Next, at a step shown in FIG. 2C, an electrode 103A comprising, forexample, Au/Ni is formed to be embedded in the recess portion 101A ofthe support board 101 and a portion of the opening portion 102A byelectrolytic plating constituting an electricity conducting path by thesupport board 101 similar to the step shown in FIG. 1B of exemplary,non-limiting Embodiment 1. In this case, when the support board 101comprises a conductive material, it is possible to form the electrode103A by electrolytic plating and it is further preferable when thesupport board 101 comprises a conductive material having low resistanceof Cu or the like.

Next, at steps shown in FIG. 2D through FIG. 2F, the insulating layer104, the via plug 105, the pattern wiring 106, the solder resist layer107, and the opening portion 107A are formed similar to the steps shownin FIG. 1C through FIG. 1E of exemplary, non-limiting Embodiment 1 toform a wiring board 100A by removing the support board 101. In the caseof the embodiment, the wiring board can be formed similar to exemplary,non-limiting Embodiment 1 other than forming the electrode 103A at therecess portion 101A and an effect similar to that in the case ofexemplary, non-limiting Embodiment 1 is achieved.

According to the wiring board 101A according to the embodiment, theelectrode 103A is constituted by a structure of being projected from thesolder resist layer 102. Therefore, when a portion of connecting theelectrode 103A and a mother board or the like is connected by the solderball, a contact area of the solder ball and the electrode 103A isincreased and therefore, an effect of improving electric connectionreliability is achieved.

Exemplary, Non-Limiting Embodiment 3

Further, FIG. 3A through FIG. 3F are views showing a method offabricating a wiring board according to exemplary, non-limitingEmbodiment 3 of the invention in accordance with a procedure thereof.Incidentally, portions in the drawings explained above are attached withthe same reference notations and an explanation thereof will be omitted.Further, portions which are not particularly explained can be formed bya method similar to that in the case of exemplary, non-limitingEmbodiment 1.

First, a step shown in FIG. 3A is similar to the step shown in FIG. 1A,the solder resist layer 102 is formed on the support board 101, and theopening portion 102A is formed at the solder resist layer 102.

Next, at a step shown in FIG. 3B, an electrode height adjusting layer103B is formed on the support board 101 exposed from the opening portion102A by, for example, an electrolytic plating method. In this case, whenthe support board 101 comprises a conductive material, the electrodeheight adjusting layer 103B can be formed by electrolytic plating and itis further preferable when the support board 101 comprises a conductivematerial having low resistance of Cu or the like.

Next, at a step shown in FIG. 3C, an electrode 103C comprising, forexample, Au/Ni is formed on the electrode height adjusting layer 103B byelectrolytic plating constituting a conductive path by the support board101 and electrode height adjusting layer 103B similar to the step shownin FIG. 1B of exemplary, non-limiting Embodiment 1.

Next, at steps shown in FIG. 3D through FIG. 3F, the insulating layer104, the via plug 105, the pattern wiring 106, the solder resist layer107, and the opening portion 107A are formed similar to the steps shownin FIG. 1C through FIG. 1E of exemplary, non-limiting Embodiment 1 and awiring board 100B is formed by removing the support board 101.

In the case of embodiment, at the step shown in FIG. 3F, when thesupport board 101 is removed by wet etching, the electrode heightadjusting layer 103B is similarly removed. Therefore, it is preferablethat the support board 101 and the electrode height adjusting layer 103Bcomprise the same material, for example, Cu or a Cu alloy.

In the case of the embodiment, the wiring board can be formed similar toexemplary, non-limiting Embodiment 1 other than the method of formingthe electrode 103C and an effect similar that in the case of exemplary,non-limiting Embodiment 1 is achieved.

According to the wiring board 100B according to the embodiment, theelectrode 103C is constituted by a structure of being recessed from aface on an outer side of the third resist layer 102.

Therefore, an effect of improving a mechanical strength of the electrode103C is achieved. Further, when the electrode 103C and a connectingterminal or the like are connected by soldering, an effect ofrestraining a contiguous electrode from being shortcircuitted by makinga solder flow out. Further, when a solder ball is bonded to theelectrode 103C, an effect of preferably mounting the solder ball isachieved.

Further, the structure of recessing the electrode from the solder resistlayer shown in the embodiment can be modified into a structure shown inexemplary, non-limiting Embodiment 4 as follows.

Exemplary, Non-Limiting Embodiment 4

FIG. 4A through FIG. 4F are views showing a method of fabricating awiring board according to exemplary, non-limiting Embodiment 4 of theinvention in accordance with a procedure thereof. Incidentally, portionsin the drawings explained above are attached with the same referencenotations and an explanation thereof will be omitted. Further, portionswhich are not explained particularly can be formed by a method similarto that in the case of exemplary, non-limiting Embodiment 3.

First, a step shown in FIG. 4A is similar to the step shown in FIG. 3A,the solder resist layer 102 is formed on the support board 101 and theopening portion 102A is formed at the solder resist layer 102.

Next, at a step shown in FIG. 4B, an electrode adjusting layer 103D isformed on the support board 101 exposed from the opening portion 102Aby, for example, an electrolytic plating method. Although in the case ofexemplary, non-limiting Embodiment 3, for example, a thickness of theelectrode height adjusting layer 103B becomes thinner than a thicknessof the solder resist layer 102, in the case of the embodiment, athickness of the electrode height adjusting layer 103D becomessubstantially the same as the thickness of the solder resist layer 102.

Next, at steps shown in FIG. 3D, similar to the step shown in FIG. 3C,an electrode 103E comprising, for example, Au/Ni is formed on theelectrode height adjusting layer 103D by electrolytic platingconstituting an electricity conducting path by the support board 101 andthe electrode height adjusting layer 103D similar to the step shown inFIG. 3C of exemplary, non-limiting Embodiment 3.

Next, at steps shown in FIG. 4D through FIG. 4F, the insulating layer104, the via plug 105, the pattern wiring 106, the solder resist layer107, and the opening portion 107A are formed similar to the steps shownin FIG. 3D through FIG. 3F of exemplary, non-limiting Embodiment 3 toform a wiring board 100C.

In the case of embodiment, when the support board 101 is removed by wetetching, the electrode height adjusting layer 103D is similarly removedsimilar to the step shown in FIG. 3F of exemplary, non-limitingEmbodiment 3. Therefore, it is preferable that the support ball 101 andthe electrode height adjusting layer 103D comprise the same material,for example, Cu.

In the case of the embodiment, the wiring board can be formed similar toexemplary, non-limiting Embodiment 3 other than the method of formingthe electrode 103E and an effect similar that in the case of exemplary,non-limiting Embodiment 3 is achieved.

According to the wiring board 100C according to the embodiment, theelectrode 103E is constituted by a structure of being recessed from theface on the outer side of the solder resist layer 102 and the electrode103E is constituted by a structure of being substantially embedded inthe insulating layer 104. That is, a total of a side wall face of theelectrode 103E is formed to be brought into contact with the insulatinglayer 104. Therefore, in addition to achieving the effect in the case ofexemplary, non-limiting Embodiment 3, there is achieved an effect offurther improving the mechanical strength of the electrode 103C incomparison with that in the case of exemplary, non-limiting Embodiment3.

Further, an area of the electrode 103E becomes larger than the area ofthe opening portion 102A. This is because when the electrode 103E isformed by electrolytic plating, the electrode 103E grows substantiallyisotropically and therefore, the electrode grows in a lateral direction.Therefore, there is constituted a structure of covering a peripheraledge portion of the electrode 103E by the solder resist layer 102 toachieve an effect of improving a strength of the electrode 103E.

Further, although according to the embodiment, an explanation has beengiven by taking an example of a case in which the thickness of theelectrode height adjusting layer is substantially the same as thethickness of the solder resist layer 102, when the thickness of theelectrode height adjusting layer is equal to or larger than thethickness of the solder resist layer 102, an effect similar to that inthe above-described case is achieved.

Exemplary, Non-Limiting Embodiment 5

Further, for example, in the cases of exemplary, non-limiting Embodiment1 through exemplary, non-limiting Embodiment 4, it is also possible touse a structure of pasting two sheets of the support boards 101 togetherto form wiring boards at the respective support boards and in that case,an efficiency of forming the wiring board can be improved.

FIG. 5 is a view showing a method of fabricating a wiring boardaccording to exemplary, non-limiting Embodiment 5 of the invention.Incidentally, portions in the drawings explained above are attached withthe same reference notations and an explanation thereof will be omitted.

FIG. 5 shows a step in correspondence with the step shown in FIG. 1D ofexemplary, non-limiting Embodiment 1. In reference to FIG. 5, accordingto the embodiment, the support board 101 is provided with a structure ofbeing pasted together with a support board 101 a. The support board 101a is formed with a solder resist layer 102 a, an electrode 103 a, aninsulating layer 104 a, a via plug 105 a, a patter wiring 106 a, asolder resist layer 107 a, and an opening portion 107 b.

The solder resist layer 101 a, the electrode 103 a, the insulating layer104 a, the via plug 105 a, the pattern wiring 106 a, the solder resistlayer 107 a, an opening portion 107 b respectively correspond to thesolder resist layer 101, the electrode 103, the insulating layer 104,the via plug 105, the pattern wiring 106, the solder resist layer 107,and the opening portion 107A and can be formed similar to the case ofexemplary, non-limiting Embodiment 1.

Further, after the step shown in the drawing, the support board 101 andthe support board 101 a are separated, a step in correspondence with thestep shown in FIG. 1E of exemplary, non-limiting Embodiment 1 isexecuted, the support board 101 and the support board 101 a are removedby wet etching, thereby, the two wiring boards can be formed.

It is apparent that the structure, the material or the like explained inthe embodiments can pertinently be modified or changed. For example, thematerial constituting the electrodes 103, 103A, 103C, 103E, 103 a or thelike is not limited to Au/Ni, for example, Au/Ni/Cu, Au/Pd/Ni,Au/Pd/Ni/Cu, Au/Pd/Ni/Pd, Au/Pd/Ni/Pd/Cu, Sn—Pb/Ni, Sn—Pb/Ni/Cu,Sn—Ag/Ni, Su—Ag/Ni/Cu, or the like can be used. Further, theabove-described materials are described successively from the metallayer constituting the surface (outer side) when the wiring board isfinished.

Further, there may be constituted a structure of increasing a rigidityof the wiring board by providing, for example, a reinforcement plate ata peripheral edge portion of the wiring board.

Exemplary, Non-Limiting Embodiment 6

Next, an explanation will be given of an example of fabricating asemiconductor device by mounting a semiconductor chip to theabove-described wiring board in reference to FIG. 6A through FIG. 6F inaccordance with a procedure thereof. However, portions in the drawingsexplained above are attached with the same reference notations and anexplanation thereof will be omitted. Further, although in the followingexample, an explanation will be given by taking an example of a case ofmounting a semiconductor chip on the mounting board described inexemplary, non-limiting Embodiment 1, a semiconductor device can befabricated by mounting a semiconductor chip also on the mounting boarddescribed in exemplary, non-limiting Embodiment 2 through exemplary,non-limiting Embodiment 5 by a similar procedure.

According to a method of fabricating a semiconductor device according tothe embodiment, first the steps shown in FIG. 1A through FIG. 1E shownin exemplary, non-limiting Embodiment 1 are executed.

Next, at a step shown in FIG. 6A, an electrode 108 comprising Au/Ni isformed on the pattern wiring 106 exposed from the opening portion 107Aof the solder resist layer 107 by, for example, a sputtering method, anelectrolytic plating method, or an electroless plating method or thelike.

Next, at a step shown in FIG. 6B, a semiconductor chip 201 formed with asemiconductor chip connecting terminal (for example, a solder ball) 202is mounted by flip chip mounting such that the semiconductor chipconnecting terminal 202 and the electrode 108 are electricallyconnected.

Next, insulation and reliability of a mounted portion are ensured bypermeating and curing an underfill 203 between the semiconductor chip201 and the solder resist layer 107.

Next, at a step shown in FIG. 6C, the support board 101 is removed by,for example, wet etching similar to the step shown in FIG. 1E.

Next, at a step shown in FIG. 6D, an external connecting terminal (forexample, solder ball) 109 is formed at the electrode 103 exposed byremoving the support board 101. Further, in the case of the embodiment,an explanation is given by taking an example of a case of fabricating asemiconductor device having a BGA (Ball Grid Array) structure andtherefore, a solder ball is formed at the electrode 103, however, theinvention is not limited thereto.

For example, according to a semiconductor device having a PGA (Pin GridArray) structure is formed with a pin as an external connectingterminal. Further, there may be constituted an LGA (Land Grid Array)structure using an electrode per se of a wiring board (semiconductordevice) as an external connecting terminal by omitting to form theexternal connecting terminal.

Next, at a step shown in FIG. 6E, by cutting the board 104, the solderresist layers 102, 107 to pieces, a semiconductor device 200 shown inFIG. 6F can be formed. In this case, a plurality of semiconductordevices can be formed by forming a structure of mounting a plurality ofthe semiconductor chips 201 on the board 104 and cutting the board 104(solder resist layers 102, 107) to cut to pieces thereafter. Further,according to the embodiment, only a single piece of the semiconductordevice is illustrated in the embodiment.

According to the method of fabricating the semiconductor deviceaccording to the embodiment, there can be fabricated the semiconductordevice achieving an effect similar to the effect described in exemplary,non-limiting Embodiment 1, capable of constituting thin-sized formationand capable of dealing with high density wiring.

Exemplary, Non-Limiting Embodiment 7

Further, the method of mounting the semiconductor chip is not limited tothe case described in exemplary, non-limiting Embodiment 6. FIG. 7 is aview showing a method of fabricating a semiconductor device according toexemplary, non-limiting Embodiment 7. However, portions in the drawingsexplained above are attached with the same reference notations and anexplanation thereof will be omitted.

According to the method of fabricating the semiconductor deviceaccording to the embodiment, first, the steps up to FIG. 6A ofexemplary, non-limiting Embodiment 6 are executed.

Next, at a step shown in FIG. 7 (in correspondence with the step of FIG.6B of exemplary, non-limiting Embodiment 6), a semiconductor chip 201Ais mounted on the solder resist layer, and the semiconductor chip 201Aand the electrode 108 are connected by a wire 202A. In this case, a filmmade of a resin may be inserted and adhered between the semiconductorchip 201A and the solder resist layer 107. Further, the semiconductorchip 201A is sealed by a resin layer 203A.

After the step of FIG. 7, when steps in correspondence with FIG. 6Cthrough FIG. 6F shown in exemplary, non-limiting Embodiment 6 arecarried out, the semiconductor apparatus can be fabricated similar tothe case of exemplary, non-limiting Embodiment 6. In this way, thesemiconductor chip can be mounted also by wire bonding (the same in thefollowing examples).

Exemplary, Non-Limiting Embodiment 8

Further, in exemplary, non-limiting Embodiment 6 or exemplary,non-limiting Embodiment 7, a method of forming the external connectingterminal (solder ball) 109 may be changed.

FIG. 8A through FIG. 8B are views showing a method of fabricating asemiconductor device according to exemplary, non-limiting Embodiment 8.However, in the drawings, portions explained above are attached with thesame reference notations and an explanation thereof will be omitted.

According to the method of fabricating a semiconductor chip according tothe embodiment, first, the step shown in FIG. 1A of exemplary,non-limiting Embodiment 1 is carried out.

Next, in a step shown in FIG. 8A, the support board 101 exposed from theopening portion 102A is etched by constituting a mask by the solderresist layer 102 to form a recess portion 101H.

Next, at a step shown in FIG. 8B, the external connecting terminal 109is formed to embed the recess portion 101H by electrolytic plating of asolder or the like by constituting an electricity conducting path by thesupport board 101. Further, the electrode 103 comprising, for example,Au/Ni is formed on the external connecting terminal 109 by electrolyticplating similar to the step shown in FIG. 1B.

In the following steps, steps similar to those of exemplary,non-limiting Embodiment 7 or exemplary, non-limiting Embodiment 8 may becarried out. That is, the steps shown in FIG. 1C through FIG. 1D andsteps shown in FIG. 6A through FIG. 6B may be carried out. Further, thestep of FIG. 7 may substitute for the step of FIG. 6B. In this case, thestep of forming the external connecting terminal shown in FIG. 6D isdispensed with. In this way, the method/step of forming the externalconnecting terminal may be changed.

Exemplary, Non-Limiting Embodiment 9

Further, although according to exemplary, non-limiting Embodiment 6through exemplary, non-limiting Embodiment 8, the semiconductor chip ismounted to a side of the solder resist layer 107, a method offabricating the semiconductor device according to the invention is notlimited thereto. For example, as explained below, the semiconductor chipmay be mounted to be connected to the electrode exposed by removing thesupport board.

FIG. 9A through FIG. 9F are views showing a method of fabricating asemiconductor device according to exemplary, non-limiting Embodiment 9.However, portions explained above are attached with the same referencenotations and an explanation thereof will be omitted.

According to the method of fabricating the semiconductor chip accordingto the embodiment, first, steps in correspondence with the step shown inFIG. 1A through FIG. 1D are carried out.

Next, at a step shown in FIG. 9A, an electrode 108F comprising Au/Ni isformed on the pattern wiring 106 exposed from the opening portion 107Aof the solder resist layer 107 by, for example, a sputtering method, anelectrolytic plating method or an electroless plating method or thelike.

Further, in the case of the embodiment, the semiconductor chip ismounted on an electrode 103F (in correspondence with the electrode 103in cases of exemplary, non-limiting Embodiments 6 through 8) andtherefore, an area of the electrode 103F becomes smaller than that ofthe electrode 103 of exemplary, non-limiting Embodiments 6 through 8.Further, an external connecting terminal (for example, a solder ball orthe like) is formed on the electrode 108F (in correspondence with theelectrode 108 in cases of exemplary, non-limiting Embodiments 6 through8) in later steps and therefore, an area of the electrode 108F becomeslarger than that of the electrode 108 of exemplary, non-limitingEmbodiments 6 through 8. Steps up to the step are made to be similar tothose in cases of exemplary, non-limiting Embodiments 6 through 8 otherthan shapes of electrodes (opening portions of solder resist incorrespondence with the electrodes).

Next, at a step shown in FIG. 9B, similar to the step shown in FIG. 1E,the support board 101 is removed by etching. Here, the electrode 103F isexposed.

Next, at a step shown in FIG. 9C, a semiconductor chip 201F formed witha semiconductor chip connecting terminal (for example, solder ball) 202Fis mounted by flip chip mounting such that the semiconductor chipconnecting terminal 202F and the electrode 103F are electricallyconnected. The semiconductor chip 201F is electrically connected to thepattern wiring 106 by way of the electrode 103F. That is, in the case ofthe embodiment, the semiconductor chip is mounted to a side of theelectrode 103F exposed by removing the support board 101.

Next, insulation and reliability of a mounted portion are ensured bypermeating and curing an underfill 203F between the semiconductor chip201F and the solder resist layer 102.

Next, at a step shown in FIG. 9D, an external connecting terminal(solder ball) 109F is formed at the electrode 108F. Further, theexternal connecting terminal 109F may be omitted to be formed or a pinmay be formed at the electrode 108F as the external connecting terminalsimilar to the case of exemplary, non-limiting Embodiment 6.

Next, a semiconductor device 200A shown in FIG. 9F can be formed bycutting the board 104, the solder resist layers 102, 107 to pieces at astep shown in FIG. 9E.

According to the method of fabricating the semiconductor deviceaccording to the embodiment, there can be fabricated the semiconductordevice achieving an effect similar to the effect described in exemplary,non-limiting Embodiment 6, capable of constituting thin-sized formationand capable of dealing with high density wiring. Further, thesemiconductor chip may be mounted by wire bonding and resin sealing asshown by exemplary, non-limiting Embodiment 7.

Exemplary, Non-Limiting Embodiment 10

Further, in exemplary, non-limiting Embodiment 9, a semiconductor chipconnecting terminal (for example, solder ball) for mounting thesemiconductor chip may be provided on a side of the board as explainedbelow.

FIG. 10A through FIG. 10F are views showing a method of fabricating asemiconductor device according to exemplary, non-limiting Embodiment 10.However, portions in the drawings explained above are attached with thesame reference notations and an explanation thereof will be omitted.

According to the method of fabricating the semiconductor deviceaccording to the embodiment, first, a step in correspondence with thestep shown in FIG. 1A of exemplary, non-limiting Embodiment 1 is carriedout. However, as explained in exemplary, non-limiting Embodiment 9, theopening portion 102A of the solder resist layer 102 is made to besmaller than that in the case of exemplary, non-limiting Embodiment 1 incorrespondence with mounting the semiconductor chip.

Next, at a step shown in FIG. 10A, a recess portion 101 h is formed byetching the support board 101 exposed from the opening portion 102A byconstituting a mask by, for example, the solder resist layer 102.

Next, at a step shown in FIG. 10B, a semiconductor chip connectingterminal (for example, solder ball) 202G is formed to embed the recessportion 101 h by electrolytic plating of a solder or the likeconstituting an electricity conducting path by the support board 101.Further, the electrode 103F comprising, for example, Au/Ni is formed onthe semiconductor chip connecting terminal 202G by electrolytic plating.

Next, at a step shown in FIG. 10C, the insulating layer 104, the viaplug 105 and the pattern wiring 106 are formed similar to the step shownin FIG. 1C of exemplary, non-limiting Embodiment 1.

Next, at a step shown in FIG. 10D, the solder resist layer 107 havingthe opening portion 107A exposing a portion of the pattern wiring 106 isformed similar to the step of FIG. 1D of exemplary, non-limitingEmbodiment 1.

Next, similar to the step of FIG. 9A of embodiment 9, the electrode 108Fcomprising Au/Ni is formed on the pattern wiring 106 exposed from theopening portion 107A of the solder resist layer 107.

Next, at a step shown in FIG. 10E, the support board 101 is removed by,for example, wet etching. Here, the solder ball 202G is exposed.

Next, at a step shown in FIG. 10F, the semiconductor chip 201G ismounted on the exposed semiconductor chip connecting terminal 202G. Inthis case, the semiconductor chip connecting terminal is formed on theside of the board and therefore, it is not necessary to form thesemiconductor chip connecting terminal on the side of the semiconductorchip.

Further, insulation and reliability of the mounted portion are ensuredby permeating and curing the underfill 203G between the semiconductorchip 201G and the solder resist layer 102.

At a step of FIG. 10F and thereafter, the semiconductor device can beformed by carrying out a step in correspondence with the step of FIG. 9Eof exemplary, non-limiting Embodiment 9.

In this way, the semiconductor chip connecting terminal (for example,solder ball) for connecting the semiconductor chip and the board canalso be formed on the side of the board.

Further, although in the method of fabricating the semiconductor deviceshown in exemplary, non-limiting Embodiment 6 through exemplary,non-limiting Embodiment 10, an explanation has been given by taking anexample of a case in which the wiring portion is constituted by a singlelayer, the invention is not limited thereto. For example, it is apparentthat the invention is applicable to a case of fabricating asemiconductor device (wiring board) having a multilayer wiring structureformed by laminating wiring portions comprising the via plugs 105 andthe pattern wirings 106 in multilayers.

In a semiconductor chip of the recent years, at a portion of connectinga semiconductor chip and a wiring board, fine pitch formation and highdensity wiring formation are progressed. Therefore, according to themethod of fabricating the wiring board according to the embodiment, thesemiconductor connecting terminal in correspondence with fine pitchformation can be formed.

Exemplary, Non-Limiting Embodiment 11

Although according to exemplary, non-limiting Embodiment 1 throughexemplary, non-limiting Embodiment 10, the solder resist layer 102 isformed on the support board 101 before removing the support board, amethod of forming the solder resist layer according to the invention isnot limited thereto. For example, as explained below, the solder resistlayer may be formed on the insulating layer after removing the supportboard.

FIG. 11A through FIG. 11F are views showing a method of fabricating awiring board according to exemplary, non-limiting Embodiment 11 of theinvention in accordance with a procedure thereof. Incidentally, portionsin the drawings explained above are attached with the same referencenotations and an explanation thereof will be omitted. Further, a portionwhich is not particularly explained can be formed by a method similar tothat in the case of exemplary, non-limiting Embodiment 11.

A step shown in FIG. 11A is similar to the steps shown in FIG. 1A andFIG. 1B, a planting resist layer 302 is formed on the support board 101,and an opening portion is formed at the plating resist layer 302. Then,by electrolytic plating constituting an electricity conducting path bythe support board 101, an electrode 103 comprising, for example, Au/Niis formed on the support board 101 to be embedded in the opening portionof the plating resist layer 302. In this case, when the support board101 comprises a conductive material, it is possible to form theelectrode 103 by electrolytic plating and it is further preferable whenthe support board 101 comprises a conductive material having lowresistance of Cu or the like.

Next, in a step shown in FIG. 11B, the plating resist layer 302 isremoved, and then an insulating layer (build up layer) 104 comprising,for example, thermosetting epoxy resin is formed on the support board101 and on the electrode 103.

At steps shown in FIG. 11C through FIG. 11E, the via plug 105, thepattern wiring 106, the solder resist layer 107, and the opening portion107A are formed similar to the steps shown in FIG. 1C through FIG. 1E ofexemplary, non-limiting Embodiment 1 to form a wiring board by removingthe support board 101. By repeatedly executing the step shown in FIG.11C before forming the solder resist layer 107, the wiring board havinga multilayer wiring structure can be formed.

Next, in a step shown in FIG. 11F, a second solder resist 308 and anopening portion are formed on the insulating layer 104 by, for example,exposure/development or a screen printing method similar to the solderresist layer 102, 107 of the above-mentioned embodiments.

In the case of the embodiment, the wiring board can be formed similar toexemplary, non-limiting Embodiment 1 other than removing the platingresist layer 302 before applying the insulating layer 104 and formingthe second solder resist layer 308 on the insulating layer 104 afterremoving the support layer 101 and an effect similar to that in the caseof exemplary, non-limiting Embodiment 1 is achieved.

Further, a semiconductor device can be fabricated by the method ofmounting a semiconductor chip to the wiring board as shown inEmbodiments 6 to 10.

Although an explanation has been given of the invention with regard topreferable embodiments, the invention is not limited to the specificembodiments but can variously be modified or changed within the gistdescribed in the scope of claims.

According to the foregoing arrangement, various advantages shown belowmay be achieved in some implementations. For example, there can beprovided the method of fabricating the wiring board capable ofconstituting thin-sized formation and capable of dealing with highdensity wiring and the method of fabricating the semiconductor deviceconstituted by mounting the semiconductor device on the wiring board.

I/We claim:
 1. A wiring board, comprising: an insulating layer; a firstelectrode embedded in the insulating layer, the first electrode having asurface exposed from a first surface of the insulating layer and a backsurface and side surfaces covered by the insulating layer; a firstsolder resist layer provided on the first surface of the insulatinglayer and having a first opening portion; a wiring portion having a viaplug provided within the insulating layer and a pattern wiring providedon a second surface of the insulating layer, the pattern wiringconnected to the back surface of the first electrode through the viaplug; a second solder resist layer provided on the second surface of theinsulating layer so as to cover the wiring portion and having a secondopening portion exposing a part of the wiring portion; and a secondelectrode formed on the part of the wiring portion exposed from thesecond opening portion, wherein a portion the surface of the firstelectrode is exposed from the first opening portion of the first solderresist layer, and a peripheral edge portion of the surface of the firstelectrode is covered by the first solder resist layer.
 2. The wiringboard according to claim 1, wherein an area of the first electrode islarger than an area of the first opening potion.
 3. The wiring boardaccording to claim 1, wherein the surface of the first electrode is on asame plane with the first surface of the insulating layer.
 4. The wiringboard according to claim 1, wherein the via plug and the pattern wiringare integrally formed by plating.
 5. The wiring board according to claim1, further comprising: a multilayer wiring structure in which at leastone insulating layer and at least one wiring portion are laminated,wherein the insulating layer constituting a first surface of themultilayer wiring structure is covered by the first solder resist layer,and the insulating layer constituting a second surface of the multilayerwiring structure, which is opposite from the first surface of themultilayer wiring structure, is covered by the second solder resistlayer.
 6. The wiring board according to claim 1, wherein the via plug isentirely embedded within a through opening defined between the first andsecond surfaces of the insulating layer.
 7. The wiring board accordingto claim 5, wherein the via plug fills an entirety of the throughopening such that side surfaces of the via plug directly abut theinsulating layer, and the via plug directly connects to the back surfaceof the first electrode.
 8. A semiconductor device, comprising: a wiringboard according to claim 1; and a semiconductor chip mounted on thewiring board, wherein the semiconductor chip is electrically connectedto the first electrode.
 9. A semiconductor device, comprising: thewiring board according to claim 1; and a semiconductor chip mounted onthe wiring board, wherein the semiconductor chip is electricallyconnected to the second electrode.